1. Field of the Invention
The present invention relates to a solid-state imaging device with a reduction in difference in level on film thickness on the boundary between an effective pixel region and a peripheral area; a method of manufacturing such a solid-state imaging device; a camera including such a solid-state imaging device; and an electronic apparatus having such a camera.
2. Description of the Related Art
Heretofore, various ideas have been proposed to improve the optical characteristics of a solid-state imaging device such as a CMOS image sensor or a CCD image sensor. For improving the sensitivity of a solid-state imaging device, for example, the device is designed to increase the amount of light incident on a photoelectric conversion element, or a photodiode.
Japanese Unexamined Patent Application Publication No. 2003-298034 and Japanese Unexamined Patent Application Publication No. H7-45805 disclose a solid-state imaging device with an optical waveguide on the light-entering side above a photodiode to improve the sensitivity of the device as a result of a increase in amount of light incident on the photodiode. The optical waveguide is formed by forming an opening on the light-entering side above the photodiode and covering and filling the opening with a material having a high refractive index.
Japanese Unexamined Patent Application Publication No. 2005-311015 describes the configuration of a CMOS solid-state imaging device having a plurality of wiring layers. In the case where a Cu wiring line and a Cu diffusion-preventing film are formed in the plurality of wiring layers, amount of light incident on a photodiode may be reduced since the Cu diffusion-preventing film reflects light to be incident on the photodiode. In Japanese Unexamined Patent Application Publication No. 2005-311015 described above, the Cu diffusion-preventing film formed above the photodiode is removed, thereby preventing a decrease in amount of light incident on the photodiode. For the removal of the Cu diffusion-preventing film formed above the photodiode, the patent document describes the step of removing the Cu diffusion-preventing film by forming an opening in the plurality of wiring layers above the photodiode. Furthermore, an optical waveguide is formed in the opening in the plurality of wiring layers.
For carrying out the step of removing a Cu diffusion-preventing film on the light-entering side above a photodiode as described in Japanese Unexamined Patent Application Publication No. 2005-311015 or the step of forming an optical waveguide on the light-entering side above a photodiode as described in Japanese Unexamined Patent Application Publication No. 2003-298034 and Japanese Unexamined Patent Application Publication No. H7-45805, additional steps of forming an opening above the photodiode and filling the opening with a material may be required.
A solid-state imaging device includes an effective pixel region, an optical black region, a peripheral circuit region, and the like. FIG. 1 illustrates a schematic configuration of a solid-state imaging device. For example, a solid-state imaging device 301, a CMOS image sensor as represented in FIG. 1, includes an imaging area 313 having an effective pixel region 311 and an optical black region 312. Furthermore, a vertical driving circuit 304, a horizontal driving circuit 306, and the like are formed in a peripheral circuit part. The imaging area 313 includes a plurality of pixels each having a photoelectric conversion element (a photodiode) and a pixel transistor (MOS transistor) in a two-dimensional matrix. The optical black region 312 is formed in part of the periphery of the effective pixel region 311 and includes a shading film to prevent light from being incident on a pixel. A signal provided as a reference signal for a black level is obtained in the optical black region 312. In the solid-state imaging device 301, light incident on the effective pixel region 311 is converted into signal electric charges and then output as a pixel signal through the peripheral circuit part.
As described above, light is incident on the photodiode in the pixels of the effective pixel region 311. In contrast, light may not be incident thereon in the pixels of the optical black region 312 on the periphery of the effective pixel region 311. Therefore, such structure as described in the above three patent documents for increasing an amount of light incident on the photodiode may be provided only in the effective pixel region 311. Specifically, an opening formed above the photodiode so as to remove a light diffusion-preventing film on the light-entering side above the photodiode, or an opening formed above the photodiode so as to make an optical waveguide on the light-entering side above the photodiode may only be required for the effective pixel region.
FIGS. 2A and 2B are cross-sectional views illustrating the process for manufacturing the solid-state imaging device 301, the CMOS image sensor, as described above. In the figure, a boundary between the effective pixel region 311 and the optical black region 312 is represented. Specifically, for example, FIGS. 2A and 2B are cross-sectional views along the line D-D shown in FIG. 1, illustrating the steps of forming openings above photodiodes PD in pixels on the effective pixel region 311.
FIGS. 2A and 2B illustrate only the photodiodes PD and a plurality of wiring layers 320 for simplified explanation. In actual, the plurality of wiring layers 320 are formed on a semiconductor substrate on which pixels each including such layers as a photodiode PD and a plurality of pixel transistors. Light is incident on the semiconductor substrate from the side where the plurality of wiring layers 320 are formed. As shown in FIGS. 2A and 2B, the plurality of wiring layers 320 include three layers of wiring lines 1M, 2M, and 3M. In addition, the wiring line 3M is provided as a shading film in the optical black region 312. Since the wiring line 3M is provided as a shading film on the optical black region 312, light may not be incident on the photodiode PD formed on the optical black region 312.
As shown in FIG. 2A, in order to increase an amount of light incident on the photodiode PD on the effective pixel region as described in the above-described three patent documents, openings 321 are formed first in an insulating interlayer 319 above the photodiodes PD on the effective pixel region 311. As shown in FIG. 2B, for example, an embedding material with a refractive index higher than that of the insulating interlayer 319 is applied to and fills the opening 321. An optical waveguide is formed in the opening 321 filled with the embedding material with a high refractive index.
As shown in FIG. 2B, in the step of forming a buried layer 322 by applying the embedding material to the opening 321, the embedding material can be simultaneously applied to the plurality of wiring layers 320 on the optical black region 312. Therefore, as shown in FIG. 2B, since no opening 321 is formed on the optical black region 312, the buried layer 322 formed on the plurality of wiring layers 320 on the optical black region 312 may be thicker than that formed in the openings 321 and on the plurality of wiring layers 320 on the effective pixel region 311. Since the buried layer 322 is unevenly applied in this manner, as shown in FIG. 2B, a difference in level on the surface of the buried layer 322 can be caused on the boundary between the effective pixel region 311 and the optical black region 312.
Likewise, FIGS. 3A to 3C illustrate an example in which openings 321 formed in the plurality of wiring layers 320 on the effective pixel region 311 are covered and filled with a buried layer 323 by the chemical vapor deposition (CVD) method or the physical vapor deposition (PVD) method. As shown in FIGS. 3A to 3C, the same structural elements as those in FIGS. 2A and 2B are designated by the same reference numerals and thus detailed description thereof will be hereinafter omitted.
As shown in FIG. 3A, if the openings 321 are filled with the buried layer 323 by the CVD method or the PVD method, the film thickness of the buried layer 323 formed as shown in FIG. 3B is almost constant. For this reason, there is a difference in density between the buried layer 323 formed on the area of openings 321 and that on the non-opening area. A difference in level on the boundary between the non-opening area and the area of openings 321 is caused. In other words, the embedding material is roughly applied to form a film on the effective region 311 on which openings 321 are formed. In contrast, the embedding material is densely applied to form a film on the optical black region 312 where any opening 321 is not formed.
Next, as shown in FIG. 3C, for planarizing the unevenness (so-called irregularity) of the buried layer 323 formed by the CVD method or the PVD method, the chemical mechanical polishing (CMP) method is employed to planarize the surface of the film made of the embedding material. However, it is difficult to planarize the surface by the CMP method. That is, the surface of the effective pixel region 311, on which the embedding material is roughly formed, and the surface of the optical black region 312, on which the embedding material is densely formed, may not be evenly planarized. As shown in FIG. 3C, a portion roughly made of the embedding material can be ground more quickly than a portion densely made thereof. Therefore, the buried layer 323 above the effective pixel region 311 is formed thinner than that formed above the optical black region 312.
In addition, in the example using a coating material as a buried layer 322 as shown in FIGS. 2A and 2B, the volume of the buried layer 322 decreases as a result of heat treatment in the step of baking after the formation of the buried layer 322. At this time, the volume of the buried layer 322 formed on the openings 321 is higher than that formed on the non-opening area by the volume of the openings. Thus, a more decrease in volume of the buried layer 322 at the time of baking can be observed on the openings 321. Accordingly, a decrease in volume after the step of baking leads to a larger difference in level between the effective pixel region 311 where openings 321 are formed densely and the optical black region 312 where any opening 321 is not formed.
Therefore, if there is a difference in level on the surface of the buried layer or a difference in film thickness thereof on the boundaries between the effective pixel region, the optical black region, and the peripheral circuit region of the solid-state imaging device, such a difference may affect any layer on or above the buried layer. Specifically, the uneven surface of the buried layer may affect the layers on or above the buried layer, such as a passivation film, a color filter, and an on-chip microlens. In addition, the difference in level or unevenness affecting the upper layer may have an influence on the inside of the effective pixel region. As a result, the optical characteristics of the pixels in the center and in periphery portions of the effective pixel region may vary, causing uneven sensitivity in an image output from the solid-state imaging device.
Japanese Unexamined Patent Application Publication No. 2001-196571 discloses a method of reducing a difference in level or film thickness between the effective pixel region and the peripheral area including the optical black region, the peripheral circuit part, and the like. The patent document describes a method of reducing a difference in level between the effective pixel region and the peripheral area by forming a concave insulating interlayer corresponding to the metal wiring line on the peripheral area. Further, Japanese Unexamined Patent Application Publication No. 2004-356585 discloses a method of applying an additional material, which can be subjected to patterning, to a portion lower in level even if there is a difference in level between the effective pixel region and the peripheral area, thereby reducing the difference in level. Furthermore, Japanese Unexamined Patent Application Publication No. 2007-165403 discloses a method of selectively etching a portion higher in level to remove the unevenness, thereby reducing the difference in level.
However, with any of the methods described in the above patent documents, for example, a decrease in difference in level between the effective pixel region and the peripheral area leads to an increase in number of steps.